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19-1478; Rev 0; 4/99
Low-Power, Serial, 14-Bit DACs with Voltage Output
General Description
The MAX5170/MAX5172 low-power, serial, voltage-output, 14-bit digital-to-analog converters (DACs) feature a precision output amplifier in a space-saving 16-pin QSOP package. The MAX5170 operates from a +5V single supply and the MAX5172 operates from a +3V single supply. Both devices draw only 280A of supply current, which reduces to 1A in shutdown. In addition, the programmable power-up reset feature allows for a user-selectable power-up output voltage of either 0 or midscale. The 3-wire serial interface is compatible with SPITM, QSPITM, and MICROWIRETM standards. An input register followed by a DAC register provides a doublebuffered input, allowing the input and DAC registers to be updated independently or simultaneously with a 16bit serial word. Additional features include software and hardware shutdown, shutdown lockout, a hardware clear pin, and a reference input capable of accepting DC and offset AC signals. These devices provide a programmable digital output pin for added functionality and a serial-data output pin for daisy-chaining. All logic inputs are TTL/CMOS-compatible and are internally buffered with Schmitt triggers to allow direct interfacing to optocouplers. The MAX5170/MAX5172 incorporate a proprietary on-chip circuit that keeps the output voltage virtually "glitch free," limiting the glitches to a few millivolts during power-up. Both devices are available in 16-pin QSOP packages and are specified for the extended (-40C to +85C) temperature range. For 100% pin-compatible DACS with internal reference, see the 13-bit MAX5130/MAX5131 and the 12bit MAX5120/MAX5121 data sheets. o 1 LSB INL o 1A Shutdown Current o "Glitch Free" Output Voltage at Power-Up o Single-Supply Operation +5V (MAX5170) +3V (MAX5172) o Full-Scale Output Range +2.048V (MAX5172, VREF = +1.25V) +4.096V (MAX5170, VREF = +2.5V ) o Rail-to-Rail(R) Output Amplifier o Adjustable Output Offset o Low THD (-80dB) in Multiplying Operation o SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface o Programmable Shutdown Mode and Power-Up Reset (0 or Midscale) o Buffered Output Capable of Driving 5k || 100pF Loads o User-Programmable Digital Output Pin Allows Serial Control of External Components o Pin-Compatible Upgrade to the 12-Bit MAX5174/MAX5176
Features
MAX5170/MAX5172
Ordering Information
PART MAX5170AEEE MAX5170BEEE MAX5172AEEE MAX5172BEEE TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 16 QSOP 16 QSOP 16 QSOP 16 QSOP INL (LSB) 1 2 2 4
Applications
Industrial Process Controls Digital Offset and Gain Adjustment Motion Control Automatic Test Equipment (ATE) Remote Industrial Controls P-Controlled Systems
Pin Configuration
TOP VIEW
OS 1 OUT 2 RS 3 PDL 4 CLR 5 CS 6 16 VDD 15 N.C. 14 REF
MAX5170 MAX5172
13 AGND 12 SHDN 11 UPO 10 DOUT 9 DGND
Functional Diagram appears at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
DIN 7 SCLK 8
QSOP
________________________________________________________________ Maxim Integrated Products
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Low-Power, Serial, 14-Bit DACs with Voltage Output MAX5170/MAX5172
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND ............................................-0.3V to +6.0V AGND to DGND.....................................................-0.3V to +0.3V Digital Inputs to DGND..........................................-0.3V to +6.0V DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V) OUT, REF to AGND ...................................-0.3V to (VDD + 0.3V) OS to AGND ...............................(AGND - 4.0V) to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8mW/C above +70C)..............667mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5170
(VDD = +5V 10%, VREF = 2.5V, OS = AGND = DGND, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity Offset Error (Note 2) Gain Error Power-Supply Rejection Ratio Output Noise Voltage Output Thermal Noise Density REFERENCE Reference Input Range Reference Input Resistance Reference -3dB Bandwidth Reference Feedthrough Signal-to-Noise Plus Distortion Ratio DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.4 V V SINAD VREF RREF VREF = 0.5Vp-p + 1.5VDC, slew-rate limited VREF = 3.6Vp-p + 1.8VDC, f = 1kHz, code = all 0s VREF = 1.5 Vp-p + 1.5VDC, f = 10kHz, code = 3FFF hex 3 0.8 200 VIN = 0 or VDD 0.001 8 1 0 18 350 -80 82 VDD - 1.4 V k kHz dB dB INL DNL VOS GE PSRR f = 100kHz RL = RL = 5k -0.6 -1.6 10 1 80 MAX5170A MAX5170B 14 1 2 1 10 4 8 120 Bits LSB LSB mV LSB V/V LSBp-p nV/Hz SYMBOL CONDITIONS MIN TYP MAX UNITS
MULTIPLYING-MODE PERFORMANCE
VIH VIL VHYS IIN CIN
V V mV A pF
2
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Low-Power, Serial, 14-Bit DACs with Voltage Output
ELECTRICAL CHARACTERISTICS--MAX5170 (continued)
(VDD = +5V 10%, VREF = 2.5V, OS = AGND = DGND, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing (Note 3) OS Pin Input Resistance Time Required to Exit Shutdown Digital Feedthrough POWER SUPPLIES Positive Supply Voltage Power-Supply Current (Note 4) Shutdown Current (Note 4) TIMING CHARACTERISTICS SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCLK Rise to DOUT Valid Propagation Delay SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse Width High tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 40 100 100 40 40 40 0 40 0 80 80 ns ns ns ns ns ns ns ns ns ns ns ns VDD IDD 4.5 0.28 1 5.5 0.4 10 V mA A CS = VDD, f SCLK = 100kHz, VSCLK = 5Vp-p SR To 0.5LSB, from 10mV to full-scale 0 80 120 40 1 0.6 18 VDD V/s s V k s nV-s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5170/MAX5172
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Low-Power, Serial, 14-Bit DACs with Voltage Output MAX5170/MAX5172
ELECTRICAL CHARACTERISTICS--MAX5172
(VDD = +2.7V to +3.6V, VREF = 1.25V, OS = AGND = DGND, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C). PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note 5) Differential Nonlinearity Offset Error (Note 2) Gain Error Power-Supply Rejection Ratio Output Noise Voltage Output Thermal Noise Density REFERENCE Reference Input Range Reference Input Resistance Reference -3dB Bandwidth Reference Feedthrough Signal-to-Noise Plus Distortion Ratio DIGITAL INPUT Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT Output High Voltage Output Low Voltage VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.4 V V VIH VIL VHYS IIN CIN VIN = 0 or VDD 200 0.001 8 1 2.2 0.8 V V mV A pF SINAD VREF RREF VREF = 0.5Vp-p + 0.75VDC, slew-rate limited VREF = 1.6Vp-p + 0.8VDC, f = 1kHz, code = all 0s VREF = 0.6Vp-p + 0.9VDC, f = 10kHz, code = 3FFF hex 0 18 350 -80 78 VDD - 1.4 V k kHz dB dB INL DNL VOS GE PSRR f = 100kHz RL = RL = 5k -0.6 -1.6 10 2 80 MAX5172A MAX5172B 14 2 4 1 10 4 8 120 Bits LSB LSB mV LSB V/V LSBp-p nV/Hz SYMBOL CONDITIONS MIN TYP MAX UNITS
MULTIPLYING-MODE PERFORMANCE
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Low-Power, Serial, 14-Bit DACs with Voltage Output
ELECTRICAL CHARACTERISTICS--MAX5172 (continued)
(VDD = 2.7V to 3.6V, VREF = 1.25V, OS = AGND = DGND, RL = 5k, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C). PARAMETER DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing (Note 3) OS Pin Input Resistance Time Required to Exit Shutdown Digital Feedthrough POWER SUPPLIES Positive Supply Voltage Power-Supply Current (Note 4) Shutdown Current (Note 4) TIMING CHARACTERISTICS SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 75 150 150 75 75 60 0 60 0 200 200 ns ns ns ns ns ns ns ns ns ns ns ns VDD IDD 2.7 0.28 1 3.6 0.4 10 V mA A CS = VDD, f SCLK = 100kHz, VSCLK = 3Vp-p SR To 0.5LSB from 10mV to full-scale 0 80 120 40 1 0.6 18 VDD V/s s V k s nV-s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5170/MAX5172
CSB Fall to SCLK Rise Setup
Time SCLK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCLK Rise to DOUT Valid Propagation Delay SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse Width High Note 1: Note 2: Note 3: Note 4: Note 5:
INL guaranteed between codes 40 and 16383. Offset is measured at the code that comes closest to 10mV. Accuracy is better than 1.0 LSB for VOUT = 10mV to VDD - 180mV. Guaranteed by PSR test on end points. RL = open and digital inputs are either VDD or DGND. INL guaranteed between codes 80 and 16383.
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Low-Power, Serial, 14-Bit DACs with Voltage Output MAX5170/MAX5172
Typical Operating Characteristics
(MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = AGND, code = 3FFF hex, TA = +25C, unless otherwise noted.)
MAX5170
NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5170/72 toc01
NO-LOAD SUPPLY CURRENT vs. TEMPERATURE
MAX5170/72 toc02
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX5170/72 toc03
330 320 NO-LOAD SUPPLY CURRENT (A) 310 300 290 280 270 260 250 240 230 4.4 4.6 4.8 5.0 5.2 SUPPLY VOLTAGE (V) 5.4
290 288 NO-LOAD SU0PPLY CURRENT (A) 286 284 282 280 278 276 274 272 270 268
1.4 1.3 SHUTDOWN CURRENT (A) 1.2 1.1 1 0.9 0.8 -50
5.6
-50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
-30
-10 10 30 50 TEMPERATURE (C)
70
90
OUTPUT VOLTAGE vs. TEMPERATURE
MAX5170/72 toc04
OUTPUT VOLTAGE vs. LOAD RESISTANCE
4.0 3.5 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 VOUT 1v/div
MAX5170/72 TOC05
DYNAMIC RESPONSE
MAX5170/72 toc06
4.0970
4.5
4,0968 OUTPUT VOLTAGE (V)
VCS 5v/div
5V 0 4.096V
4.0966
4.0964
4.0962
10mV
4.0960 -50
0 -30 -10 10 30 50 TEMPERATURE (C) 70 90 10 100 1k RL () 10k 100k 2s/div
DYNAMIC RESPONSE
MAX5170/72 toc07
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX5170/72 toc08
REFERENCE FEEDTHROUGH
VREF = 1.8VDC + 3.6Vp-p at f = 1kHz VOUT/VREF
MAX5170/72 toc9
-75 5V 0 THD + NOISE (dB) 4.096V -76 -77 -78 -79 -80 -81 -82 10mV -83 -84 10 100 1k 10k FREQUENCY (Hz)
0
VCS 5V/div
VOUT 1V/div
12.5dB/div
2s/div
100k
20
FREQUENCY (Hz)
10k
6
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Low-Power, Serial, 14-Bit DACs with Voltage Output
Typical Operating Characteristics (continued)
(MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = AGND, code = 3FFF hex, TA = +25C, unless otherwise noted.)
MAX5170/MAX5172
MAX5170
FFT PLOT
MAX5170/72 toc10
MAJOR-CARRY TRANSITION
MAX5170/72 toc11
DIGITAL FEEDTHROUGH
MAX5170/72 toc12
0 VREF = 1.25VDC + 1.13Vp-p, at f = 10kHz
VCS 2V/div
VOUT 2mV/div VOUT/VREF 12.5dB/div VOUT 100mV/div ACCOUPLED VSCLK 5V/div
20
FREQUENCY (Hz)
100k
5s/div
400ns/div
REFERENCE INPUT FREQUENCY RESPONSE
MAX5170/72 toc13
START-UP GLITCH
MAX5170/72 toc14
5 0 -5 GAIN (dB) -10 -15 -20 -25 0 500 1000 1500 2000 FREQUENCY (kHz) 2500
VDD 1V/div
VREF = 0.67Vp-p + 1.5VDC
VOUT 10mV/div AC-COUPLED
3000
50ms/div
MAX5172
MAX5170/72 toc15
295 NO-LOAD SUPPLY CURRENT (A) 290 285 280 275 270 265 260 255 250
MAX5170/72 toc16
NO-LOAD SUPPLY CURRENT (A)
290 285 280 275 270 275 260 -50
0.58 SUPPLY CURRENT (A) 0.56 0.54 0.52 0.5 0.48 0.46 0.44 -50
2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 SUPPLY VOLTAGE (V)
-30
-10 10 30 50 TEMPERATURE (C)
70
90
-30
-10 10 30 50 TEMPERATURE (C)
70
90
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MAX5170/72 toc17
300
NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE
295
NO-LOAD SUPPLY CURRENT vs. TEMPERATURE
0.60
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
Low-Power, Serial, 14-Bit DACs with Voltage Output MAX5170/MAX5172
Typical Operating Characteristics (continued)
(MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = AGND, code = 3FFF hex, TA = +25C, unless otherwise noted.)
MAX5172
OUTPUT VOLTAGE vs. TEMPERATURE
MAX5170/72 toc18
OUTPUT VOLTAGE vs. LOAD RESISTANCE
MAX5170/72 toc19
DYNAMIC RESPONSE
MAX5170/72 toc20
2.0490
2.5 2.0 OUTPUT VOLTAGE (V) 1.5 1.0 0.5 0 -0.5
2.0488 OUTPUT VOLTAGE (V)
VCS 3V/div
3V 0 2.048V
2.0486
2.0484
VOUT 500mV/div
2.0482
10mV 2s/div
2.0480 -50
-30
-10 10 30 50 TEMPERATURE (C)
70
90
10
100
1k RL ()
10k
100k
DYNAMIC RESPONSE
MAX5170/72 toc21
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX5170/72 toc22
REFERENCE FEEDTHROUGH
VREF = 0.8VDC + 1.6Vp-p at f = 1kHz
MAX5170/72 toc23
-78.0 3V 0 2.048V THD + NOISE (dB) -78.5 -79.0 -79.5 -80.0 -80.5 -81.0 10mV -81.5 -82.0
0
VCS 3V/div
VOUT 500mV/div
VOUT/VREF 12.5dB/div
2s/div
10
100
1k 10k FREQUENCY (Hz)
100k
20
FREQUENCY (Hz)
10k
FFT PLOT
MAX5170/72 toc24
MAJOR-CARRY TRANSITION
MAX5170/72 toc25
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5170/72 toc26
0 VREF = 0.9VDC + 0.424Vp-p at f = 10kHz
CS 2V/div
SCLK 2V/div
VOUT/VREF 12.5dB/div OUT 100mV/div OUT 500V/div
20
FREQUENCY (Hz)
100k AC-COUPLED
5s/div AC-COUPLED
2s/div
8
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Low-Power, Serial, 14-Bit DACs with Voltage Output
Typical Operating Characteristics (continued)
(MAX5170: VDD = +5V, VREF = 2.5V; MAX5172: VDD = +3V, VREF = 1.25V; CL = 100pF, OS = GND, code = 3FFF hex, TA = +25C, unless otherwise noted.)
MAX5170/MAX5172
MAX5172
REFERENCE INPUT FREQUENCY RESPONSE
MAX5170/72 toc27
START-UP GLITCH
MAX5170/72 toc28
5 0 -5 GAIN (dB) -10 -15 -20 -25 -30 0 500 1000 1500 2000 FREQUENCY (kHz) 2500 VREF = 0.67Vp-p + 0.75VDC
VDD 1V/div
VOUT 10mV/div
3000
50ms/div AC-COUPLED
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME OS OUT RS PDL CLR CS DIN SCLK DGND DOUT UPO SHDN AGND REF N.C. VDD FUNCTION Offset Adjustment. Connect to AGND for no offset. Voltage Output. High impedance when in shutdown. The output voltage is limited to VDD. Reset Mode Select (digital input). Connect to VDD to select midscale reset output voltage. Connect to DGND to select 0 reset output voltage. Power-Down Lockout (digital input). Connect to VDD to allow shutdown. Connect to DGND to disable software and hardware shutdown. Clear DAC (digital input). Clears the DAC to either zero or midscale as determined by RS. Chip Select Input (digital input). DIN ignored when CS is high. Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK. Serial Clock Input (digital input) Digital Ground Serial-Data Output User-Programmable Output. State is set by the serial input. Shutdown (digital input). Pulling SHDN high when PDL = VDD places the chip in shutdown with a maximum shutdown current of 10A. Analog Ground Reference Input. Maximum VREF is VDD - 1.4V. No Connection Positive Supply. Bypass to AGND with a 4.7F capacitor in parallel with a 0.1F capacitor.
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Low-Power, Serial, 14-Bit DACs with Voltage Output MAX5170/MAX5172
Detailed Description
The MAX5170/MAX5172 14-bit, serial, voltage-output DACs operate with a 3-wire serial interface. These devices include a 16-bit shift register and a doublebuffered input composed of an input register and a DAC register (see Functional Diagram). In addition, these devices employ a rail-to-rail output amplifier and internally trimmed resistors to provide a gain of +1.638V/V, maximizing the output voltage swing. The MAX5170/MAX5172's offset adjust pin allows for a DC shift in the DAC output. The DACs are designed with an inverted R-2R ladder network (Figure 1) which produces a weighted voltage proportional to the reference voltage.
R OS
R R R R OUT
2R
2R D0
2R D10
2R D11
2R D12
REF AGND SHOWN FOR ALL 1s ON DAC
Reference Inputs
The reference input accepts both AC and DC values with a voltage range extending from 0 to VDD - 1.4V. The following equation represents the resulting output voltage: VOUT = VREF
* N * Gain 16384
Figure 1. Simplified DAC Circuit Diagram
reloading the DAC register from the shift register, by simultaneously loading the input and DAC registers, or by toggling PDL. When returning from shutdown, wait 40s for the output to settle.
where N is the numeric value of the DAC's binary input code (0 to 16383), VREF is the reference voltage, and Gain is the internal set voltage gain (+1.638V/V if OS = AGND). The maximum output voltage is VDD. The reference pin has a minimum impedance of 18k and is code dependent.
Power-Down Lockout Power-Down Lockout disables the software/hardware shutdown mode. A high-to-low transition brings the device out of shutdown and returns the output to its previous state. Shutdown Pulling SHDN high while PDL is high places the MAX5170/MAX5172 in shutdown. Pulling SHDN low will not return the device to normal operation. A high-to-low transition on PDL or an appropriate command from the serial data line (see Table 1 for commands) is required to exit shutdown.
Output Amplifier
With OS connected to AGND, the output amplifier employs an internal, trimmed resistor-divider setting the gain to +1.638V/V and minimizing gain error. The output amplifier has a typical slew rate of 0.6V/s and settles to 0.5LSB from a full-scale transition within 18s, when loaded with 5k in parallel with 100pF. Loads less than 2k degrade performance. For alternative output amplifier setups, refer to the Applications Information section.
Serial-Interface
The MAX5170/MAX5172 3-wire serial interface is compatible with SPI, QSPI (Figure 2) and MICROWIRE (Figure 3) interface standards. The 16-bit serial input word consists of two control bits and 14 bits of data (MSB to LSB). The control bits determine the MAX5170/MAX5172's operation as outlined in Table 1. The MAX5170/ MAX5172's digital inputs are double buffered, which allows any of the following: * Loading the input register without updating the DAC register * Updating the DAC register from the input register * Updating the input and DAC registers simultaneously.
Shutdown Mode
The MAX5170/MAX5172 feature a software- and hardware-programmable shutdown mode that reduces the typical supply current to 1A. Enter shutdown by writing the appropriate input-control word as shown in Table 1 or by using the hardware shutdown. In shutdown mode, the reference input and the amplifier output become high-impedance and the serial interface remains active. Data in the input register is saved, allowing the MAX5170/MAX5172 to recall the prior output state when returning to normal operation. Exit shutdown by
10
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Low-Power, Serial, 14-Bit DACs with Voltage Output
+5V
SS DIN MOSI
MAX5170 MAX5172
SCLK
SCK
SPI/QSPI PORT
CS
I/O
CPOL = 0, CPHA = 0
Figure 2. Connections for SPI and QSPI Interface
The MAX5170/MAX5172 accepts one 16-bit packet or two 8-bit packets sent while CS remains low. The MAX5170/MAX5172 allow the following to be configured: * Clock edge on which serial data output (DOUT) is clocked out * State of the user-programmable logic output * Configuration of the reset state. Specific commands for setting these are shown in Table 1. The general timing diagram in Figure 4 illustrates how the MAX5170/MAX5172 acquire data. CS must go low at least tCSS before the rising edge of the serial clock (SCLK). With CS low, data is clocked into the register on the rising edge of SCLK. The maximum serial clock frequency guaranteed for proper operation is 10MHz for MAX5170 and 6MHz for MAX5172. See Figure 5 for a detailed timing diagram of the serial interface.
MAX5170/MAX5172
Serial Data Output (DOUT)
SCLK SK
MAX5170 MAX5172
DIN
SO
MICROWIRE PORT
CS
I/O
The serial-data output, DOUT, is the internal shift register's output and allows for daisy-chaining of multiple devices as well as data readback (see Applications Information). By default upon start-up, data shifts out of DOUT on the serial clock's rising edge (Mode 0) and provides a lag of 16 clock cycles, thus maintaining SPI, QSPI, and MICROWIRE compatibility. However, if the device is programmed for Mode 1, the output data lags DIN by 16.5 clock cycles and is clocked out on the serial clock's rising edge. During shutdown, DOUT retains its last digital state prior to shutdown.
Figure 3. Connections for MICROWIRE Interface Standards
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD C1 0 0 1 1 1 1 1 1 1 C0 0 1 0 1 1 1 1 1 1 D11..................D0 14-bit DAC data 14-bit DAC data x x x xxx xxxx xxxx 0 0 x xxx xxxx xxxx 0 1 x xxx xxxx xxxx 1 0 0 xxx xxxx xxxx 1 0 1 xxx xxxx xxxx 1 1 0 xxx xxxx xxxx 1 1 1 xxx xxxx xxxx FUNCTION Load input register; DAC registers are unchanged. Load input register; DAC registers are updated (start-up DAC with new data). Update DAC register from input register (start-up DAC with data previously stored in the input registers). No operation (NOP). Shut down DAC (provided PDL = 1). UPO goes low (default). UPO goes high. Mode 1, DOUT clocked out on SCLK's rising edge. Mode 0, DOUT clocked out on SCLK's falling edge (default). 11
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Low-Power, Serial, 14-Bit DACs with Voltage Output MAX5170/MAX5172
CS COMMAND EXECUTED 1 DIN C2 C1 C0 D9 D8 D7 D6 8 D5 D4 9 D3 D2 D1 D0 S2 S1 16 S0
SCLK
Figure 4. Serial-Interface Timing Diagram
tCSW CS tCSO SCLK tCH tCP DIN tDS DOUT tD01 tD02 tDH tCL tCSS tCSH tCS1
Figure 5. Detailed Serial-Interface Timing Diagram
User-Programmable Logic Output (UPO)
The UPO allows control of an external device through the serial interface, thereby reducing the number of microcontroller I/O pins required. During power-down, this output retains its digital state prior to shutdown. When CLR is pulled low, UPO resets to its programmed default state. See Table 1 for specific commands to control the UPO.
Reset (RS) and Clear (CLR)
The MAX5170/MAX5172 offers a clear pin which resets the output voltage. If RS = DGND, then CLR resets the output voltage to the minimum voltage (0 if OS = AGND). If RS = VDD, then CLR resets the output voltage to midscale. In either case, CLR resets UPO to its programmed default state.
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Low-Power, Serial, 14-Bit DACs with Voltage Output
Applications Information
Unipolar Output
Figure 6 shows the MAX5170/MAX5172 configured for unipolar, rail-to-rail operation with a gain of +1.638V/V. Table 2 lists the codes for unipolar output voltages. The maximum output voltage is limited to VDD. Use the OS pin to introduce an offset voltage as shown in Figure 7 and described in the Offset and Buffer Configurations section.
+5V/+3V REF VDD VOS OS
MAX5170/MAX5172
MAX5170 MAX5172
DAC AGND DGND OUT
Bipolar Output
Figure 8 shows the MAX5170/MAX5172 configured for bipolar output operation. The output voltage is given by the following equation (OS = AGND): 2 *N VOUT = VREF - 1 16,384 where N represents the numeric value of the DAC's binary input code, VREF is the voltage of the external reference. Table 3 shows digital codes and the corresponding output voltage for Figure 8's circuit.
Figure 7. Setting OS for Output Offset
REF
+5V/+3V
10k OS
10k
+5V/+3V REF VDD
OS
VDD
MAX5170 MAX5172
DAC OUT DGND AGND OUT
V+
MAX5170 MAX5172
DAC AGND DGND
VOUT
V-
Figure 8. Bipolar Output Circuit Figure 6. Unipolar Output Circuit (Rail-to-Rail)
Table 2. Unipolar Code Table (Circuit of Figure 6)
DAC CONTENTS MSB LSB 11 1111 1111 1111 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0001 00 0000 0000 0000 ANALOG OUTPUT +VREF (16383/16384) * 1.638 +VREF (8193/16384) * 1.638 +VREF (8192/16384) * 1.638 +VREF (8191/16384) * 1.638 +VREF (1/16384) * 1.638 0
Table 3. Bipolar Code Table (Circuit of Figure 8)
DAC CONTENTS MSB LSB 11 1111 1111 1111 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0001 00 0000 0000 0000 ANALOG OUTPUT +VREF [(2 * 16383/16384) - 1] +VREF [(2 * 8193/16384) - 1] +VREF [(2 * 8192/16384) - 1] +VREF [(2 * 8191/16384) - 1] +VREF [(2 * 1/16384) - 1] -VREF 13
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Low-Power, Serial, 14-Bit DACs with Voltage Output MAX5170/MAX5172
Offset and Buffer Configurations
The simple circuit of Figure 7 illustrates how to introduce an offset to the output voltage. The amount of offset introduced by a voltage at the OS pin is shown in the following equation: VOFFSET = VOS * (1 - Gain) where Gain = 1.638. However, the total output voltage of the device cannot exceed VDD regardless of the voltage on the OS pin. To set the gain of the output amplifier to 1, connect OS to OUT.
Power-Supply and Layout Considerations
Wire-wrap boards are not recommended. For optimum system performance, use printed circuit boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source. Connect DGND and AGND pins together at the IC. The best ground connection is achieved by connecting the DAC's DGND and AGND pins together and connecting that point to the system analog ground plane. This is useful because if the DAC's DGND is connected to the system digital ground, digital noise may get through to the DAC's analog portion. Bypass the power supply with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND. Minimize their lead lengths to reduce inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. To maintain INL and DNL performance as well as gain drift, it is extremely important to provide the lowest possible reference output impedance at the DAC reference input pin. INL degrades if the series resistance on REF pin exceeds 0.1. The same consideration must be made for the AGND pin.
Daisy-Chaining Devices
The serial data output pin (DOUT) allows multiple MAX5170/MAX5172s to be daisy-chained together, as shown in Figure 9. The advantage of this is that only two lines are needed to control all the DACs on the line. The disadvantage is that it takes n commands to program the DACs. Figure 10 shows several MAX5170/MAX5172s sharing one common DIN signal line. In this configuration, the data bus is common to all devices. However, more I/O lines are required for this configuration because each device requires a dedicated CS line. The advantage of this configuration is that only one command is needed to program any DAC.
Using an AC Reference
The MAX5170/MAX5172 accepts reference voltages with AC components as long as the reference voltage remains between 0 and VDD - 1.4V. Figure 11 shows a technique for applying an offset sine wave signal to REF. The reference voltage must remain above AGND.
SCLK
SCLK
SCLK
MAX5170 MAX5172
DIN CS DOUT DIN CS
MAX5170 MAX5172
DOUT DIN CS
MAX5170 MAX5172
DOUT
TO OTHER SERIAL DEVICES
Figure 9. Daisy-Chaining MAX5170/MAX5172 Devices
14
______________________________________________________________________________________
Low-Power, Serial, 14-Bit DACs with Voltage Output MAX5170/MAX5172
DIN SCLK CS1 CS2 CS3 TO OTHER SERIAL DEVICES
CS
CS
CS
MAX5170 MAX5172
SCLK DIN SCLK DIN
MAX5170 MAX5172
SCLK DIN
MAX5170 MAX5172
Figure 10. Multiple MAX5170/MAX5172s Sharing Common DIN and SCLK Lines
+5V/ +3V +5V/+3V R1 AC REFERENCE INPUT
Chip Information
TRANSISTOR COUNT: 3457
MAX495
500mVp-p
R2
REF
VDD
OS
DAC
OUT
AGND
MAX5170 MAX5172
GND
Figure 11. AC Reference Input Circuit
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15
Low-Power, Serial, 14-Bit DACs with Voltage Output MAX5170/MAX5172
Functional Diagram
CS DIN SCLK VDD AGND DGND
PDL SHDN
SERIAL CONTROL
16-BIT SHIFT REGISTER
DOUT LOGIC OUTPUT UPO OS
RS CLR
DECODE CONTROL
MAX5170 MAX5172
INPUT REGISTER
DAC REGISTER
DAC
OUT
REF
Package Information
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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